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400 msps 14-bit, 1.8 v cmos direct digital synthesizer ad9951 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 400 msps int e r n al clock speed integrated 14-bit dac 32-bit tuning w o rd phase noise C 120 dbc/hz @ 1 khz offset ( d a c output) excellent dyna mic performance >80 db sfdr @ 160 m hz ( 10 0 kh z offset) a out serial i/o contr o l 1.8 v power supply software and h a rdware controlled power-down 48-lea d tqfp/e p package support for 5 v input le vels on most digital in puts pll refclk multiplier ( 4 to 20) internal oscilla tor, can be driven by a s i ngle c r ystal phase modul a t i on capability multichip synchronization a pplic a t io ns agile lo frequency synthesis programmable clock generators test and meas urement e q uip m ent a c ou sto-optic d e v i ce d r iv ers func ti onal bl oc k di a g ram cos(x) control registers oscillator/buffer sync enable i/o update dac_r set dds core phase offset phase accumulator z ?1 z ?1 iout iout osk pwrdwnctl refclk refclk crystal out i/o port ps<1:0> dds clock fre q ue ncy tuning word cle a r p has e accumulator amp l itude sc a l e fa c t or dac system clock system clock sync_in sync_clk reset timing and control logic 4 ?20 clock multiplier 4 ad9951 32 32 14 14 19 14 0 m u x m u x 03359-0-001 fi g u r e 1 .
ad9951 rev. 0 | page 2 of 28 table of contents general description ......................................................................... 3 ad9951electrical sp ecifications ................................................ 4 absolute maximum ratings............................................................ 6 pin configuration............................................................................. 7 pin function descriptions .............................................................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 component blocks ..................................................................... 12 modes of operation ................................................................... 17 programming ad9951 features............................................... 17 serial port operation................................................................. 20 instruction byte .......................................................................... 22 serial interface port pin description....................................... 22 msb/lsb transfers .................................................................... 22 suggested application circuits..................................................... 24 outline dimensions ....................................................................... 25 esd caution................................................................................ 25 ordering guide .......................................................................... 25 revision history revision 0: initial version
ad9951 rev. 0 | page 3 of 28 general description the ad9951 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400 msps. the ad9951 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 mhz. the ad9951 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the ad9951 via a serial i/o port. the ad9951 is specified to operate over the extended industrial temperature range of C40c to +105c.
ad9951 rev. 0 | page 4 of 28 ad9951electrical specifications table 1. unless otherwise noted, avdd, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%, r set = 3.92 k?, external reference clock frequency = 20 mhz with refclk multiplier enabled at 20 . dac output must be referenced to avdd, not agnd. parameter temp min typ max unit ref clock input characteristics frequency range refclk multiplier disabled full 1 400 mhz refclk multiplier enabled at 4 full 20 100 mhz refclk multiplier enabled at 20 full 4 20 mhz input capacitance 25c 3 pf input impedance 25c 1.5 k? duty cycle 25c 50 % duty cycle with refclk multiplier enabled 25c 35 65 % refclk input power 1 full C15 0 +3 dbm dac output characteristics resolution 14 bits full-scale output current 25c 5 10 15 ma gain error 25c C10 +10 %fs output offset 25c 0.6 a differential nonlinearity 25c 1 lsb integral nonlinearity 25c 2 lsb output capacitance 25c 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 25c C105 dbc/hz refclk multiplier enabled @ 4 25c C115 dbc/hz refclk multiplier disabled 25c C132 dbc/hz voltage compliance range 25c avdd C 0.5 avdd + 0.5 v wideband sfdr 1 mhz to 10 mhz analog out 25c 73 dbc 10 mhz to 40 mhz analog out 25c 67 dbc 40 mhz to 80 mhz analog out 25c 62 dbc 80 mhz to 120 mhz analog out 25c 58 dbc 120 mhz to 160 mhz analog out 25c 52 dbc narrow-band sfdr 40 mhz analog out (1 mhz) 25c 87 dbc 40 mhz analog out (250 khz) 25c 89 dbc 40 mhz analog out (50 khz) 25c 91 dbc 40 mhz analog out (10 khz) 25c 93 dbc 80 mhz analog out (1 mhz) 25c 85 dbc 80 mhz analog out (250 khz) 25c 87 dbc 80 mhz analog out (50 khz) 25c 89 dbc 80 mhz analog out (10 khz) 25c 91 dbc 120 mhz analog out (1 mhz) 25c 83 dbc 120 mhz analog out (250 khz) 25c 85 dbc 120 mhz analog out (50 khz) 25c 87 dbc 120 mhz analog out (10 khz) 25c 89 dbc 160 mhz analog out (1 mhz) 25c 81 dbc 160 mhz analog out (250 khz) 25c 83 dbc 160 mhz analog out (50 khz) 25c 85 dbc 160 mhz analog out (10 khz) 25c 87 dbc
ad9951 rev. 0 | page 5 of 28 parameter temp min typ max unit timing characteristics serial control bus maximum frequency full 25 mbps minimum clock pulse width low full 7 ns minimum clock pulse width high full 7 ns maximum clock rise/fall time full 2 ns minimum data setup time dv dd_i/o = 3.3 v full 3 ns minimum data setup time dv dd_i/o = 1.8 v full 5 ns minimum data hold time full 0 ns maximum data valid time full 25 ns wake-up time 2 full 1 ms minimum reset pulse width high full 5 sysclk cycles 3 i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 4 ns i/o update to sync_clk setup time dvdd_i/o = 3.3 v full 6 ns i/o update, sync_clk hold time full 0 ns latency i/o update to frequency change pr op delay 25c 24 sysclk cycles i/o update to phase offset change prop delay 25c 24 sysclk cycles i/o update to amplitude change pr op delay 25c 16 sysclk cycles cmos logic inputs logic 1 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 1.25 v logic 0 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 0.6 v logic 1 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 2.2 v logic 0 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 0.8 v logic 1 current 25c 3 12 a logic 0 current 25c 12 a input capacitance 25c 2 pf cmos logic outputs (1 ma load) dvdd_i/o = 1.8 v logic 1 voltage 25c 1.35 v logic 0 voltage 25c 0.4 v cmos logic outputs (1 ma load) dvdd_i/o = 3.3 v logic 1 voltage 25c 2.8 v logic 0 voltage 25c 0.4 v power consumption (avdd = dvdd = 1.8 v) single-tone mode 25c 162 171 mw rapid power-down mode 25c 150 160 mw full-sleep mode 25c 20 27 mw synchronization function 4 maximum sync clock rate (dvdd_i/o = 1.8 v) 25c 62.5 mhz maximum sync clock rate (dvdd_i/o = 3.3 v) 25c 100 mhz sync_clk alignment resolution 5 25c 1 sysclk cycles 1 to achieve the best possible phase noise, the largest amplitude clock possible should be used. reducing the clock input amplit ude will reduce the phase noise per- formance of the device. 2 wake-up time refers to the recovery from analog power-do wn modes (see the section). the longest time requir ed is for the reference clock multiplier pll to relock to the reference. the wake-up time assumes there is no capacitor on dacbp and that the recommended pll loop filter values are used. power-down functions of the ad9951 3 sysclk cycle refers to the actual clock frequency used on-chip by the dds. if the reference clock multiplier is used to multip ly the external reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplication factor. if the reference clock multiplier is not used, the sysclk fre- quency is the same as the external reference clock frequency. 4 sync_clk = ? sysclk rate. for sync_clk rates 50 mhz, the high speed sync enable bit, cfr2<11>, should be set. 5 this parameter indicates that the digital synchronization feature canno t overcome phase delays (timing skew) between system cl ock rising edges. if the system clock edges are aligned, the synchronizat ion function should not increase the skew between the two edges.
ad9951 rev. 0 | page 6 of 2 8 absolute maximum ratings table 2. p a r a m e t e r r a t i n g maximum junction temperature 150c dvdd_i/o (pin 43) 4 v avdd, dvdd 2 v digital input voltage (dvdd_i/o = 3.3 v) C0.7 v to +5.25 v digital input voltage ( d vdd_i/o = 1.8 v) C0.7 v to +2.2 v digital output c u rrent 5 ma storage temperature C65c to +150c operating tem p erature C40c to +105c lead temperature (10 sec soldering) 300c ja 3 8 c / w jc 15c/w s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t - i n g on ly a n d f u nc t i on a l o p e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c - t i o n o f t h is sp e c if ica t ion is n o t i m plie d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . io u t io u t m u s t t e rm i n at e outputs to avdd. do not exceed the output voltage compliance rating. da c o ut p u t s dv d d _ i / o in p u t dig i t a l inputs av o i d o v e r dr i v i n g digital inputs. forward biasing esd diodes may couple digital noise onto power pins. 03374-0-032 f i gure 2 . e q ui v a lent input a n d o u tput ci rcui ts
ad9951 rev. 0 | page 7 of 2 8 pin conf iguration 43 42 41 40 39 38 37 48 47 46 45 44 13 15 16 17 18 19 20 21 22 23 24 i/o update dvdd dgnd avdd agnd avdd agnd osc/refclk osc/refclk crystal out clkmodeselect loop_filter agnd av dd agnd av dd agnd av dd iout av dd iout dacbp dac_ r set agnd osk dgnd dgnd s y nc_ cl k s y nc_ in dv dd_ i/o sc lk dgnd sd io sd o cs iosyn c reset pwrdwnctl dvdd dgnd agnd agnd agnd avdd agnd avdd agnd avdd ad9951 top view (not to scale) 14 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 03359-0-002 f i g u re 3. 48-l e ad tqfp/e p n o t e tha t the exp o s e d pa d d l e o n the b o t t o m o f the pack age f o rms an el e c tr i c a l co nne c ti o n f o r the d a c and m u st b e a t tache d t o ana l og g r o u nd. n o t e tha t p i n 43, d v d d _i/o , c a n b e p o w e r e d t o 1. 8 v o r 3. 3 v ; h o w e v e r , t h e d v d d p i ns (p in 2 and p i n 34) c a n o n ly b e p o w e r e d t o 1.8 v .
ad9951 rev. 0 | page 8 of 28 pin function descriptions table 3. pin function descriptions48-lead tqfp/ep pin no. mnemonic i/o description 1 i/o update i the rising edge transfers the contents of the inte rnal buffer memory to the i/o registers. this pin must be set up and held arou nd the sync_clk output signal. 2, 34 dvdd i digital power supply pins (1.8 v). 3, 33, 42, 47, 48 dgnd i digital power ground pins. 4, 6, 13, 16, 18, 19, 25, 27, 29 avdd i analog power supply pins (1.8 v). 5, 7, 14, 15, 17, 22, 26, 28, 30, 31, 32 agnd i analog power ground pins. 8 osc / refclk i complementary reference clock/oscillator input. when the refclk port is operated in single- ended mode, refclkb should be decoup led to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input. see clock in put section for details on the oscillator/refclk operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. when high, th e oscillator section is enabled. when low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the extern al zero compensation network of the refclk multipliers pll loop filter. the network consists of a 1 k? resistor in series with a 0.1 f capacitor tied to avdd. 20 iout o complementary dac output. should be bias ed through a resistor to avdd, not agnd. 21 iout o dac output. should be biased through a resistor to avdd, not agnd. 23 dacbp i dac biasline decoupling pin. 24 dac_r set i a resistor (3.92 k? nominal) connected from agnd to dac_r set establishes the reference current for the dac. 35 pwrdwnctl i input pin used as an external power-down cont rol (see table 8 for details). 36 reset i active high hardware reset pin. assertion of the reset pin forces the ad9951 to the initial state, as described in the i/o port register map. 37 iosync i asynchronous active high reset of the serial port controller. when high, the current i/o operation is immediately terminated, enabling a new i/o operation to commence once iosync is returned low. if unused, ground this pi n; do not allow this pin to float. 38 sdo o when operating the i/o port as a 3-wire serial port, this pin serves as the se rial data output. when operated as a 2-wire serial port, this pi n is unused and can be left unconnected. 39 cs i this pin functions as an active low chip select that allows multiple devices to share the i/o bus. 40 sclk i this pin functions as the serial data clock for i/o operations. 41 sdio i/o when operating the i/o port as a 3-wire serial port, this pin serves as the se rial data input, only. when operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 43 dvdd_i/o i digital power supply (for i/o cells only, 3.3 v). 44 sync_in i input signal used to synchronize multiple ad9951s. this input is connected to the sync_clk output of a master ad9951. 45 sync_clk o clock output pin that serves as a synchronizer for external hardware. 46 osk i input pin used to control the direction of the shaped on-off keying function when programmed for operation. osk is synchronous to the sync_clk pin. when osk is not programmed, this pin should be tied to dgnd. <49> agnd i the exposed paddle on the bottom of the package is a ground connection for the dac and must be attached to agnd in any board layout.
ad9951 rev. 0 | page 9 of 2 8 typical perf orm ance cha r acte ristics center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 98.0mhz ? 70.68db 1 1r 03374-0-016 marker 100.000000mhz ? 70.68db fi g u r e 4 . f ou t = 1 m h z fclk = 40 0 ms p s , wbsf dr center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ? 69.12db 1 1r 03374-0-017 marker 80.000000mhz ? 69.12db fi g u r e 5 . f ou t = 1 0 mh z, fclk = 40 0 m s ps, wbsfdr center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ? 68.44db 1 1r 03374-0-018 marker 40.000000mhz ?68.44db fi g u r e 6 . f ou t = 4 0 mh z, fclk = 40 0 m s ps, wbsfdr center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ? 61.55db 1 1r 03374-0-019 marker 80.000000mhz ? 61.55db fi g u r e 7 . f ou t = 80 m h z fclk = 40 0 m s ps, wbsfdr center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 40.0mhz ?56.2db 1 1r 03374-0-020 marker 40.000000mhz ? 56.2db fi g u r e 8 f ou t = 12 0 mhz , f c lk = 4 0 0 m s p s , w b sfdr center 100mhz #res bw 3khz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ? 53.17db 1 1r 03374-0-021 marker 80.000000mhz ? 53.17db fi g u r e 9 . f ou t = 160 mhz , f c lk = 40 0 msp s , w b sfdr
ad9951 rev. 0 | page 10 of 28 center 1.105mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ? 4dbm pea k log 10db/ atten 10db mkr1 1.105mhz ?5.679dbm 1 03374-0-022 marker 1.105000mhz ? 5.679dbm f i g u re 10. f ou t = 1. 1 m h z, fclk = 40 0 m s ps, nbsfdr , 1 m h z center 10mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 85khz ? 93.01db 1 1r 03374-0-023 marker 40.000000mhz ? 56.2db f i g u re 11. f ou t = 10 mhz , f c lk = 40 0 msp s , nbsfdr, 1 mhz center 39.9mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 39.905mhz ?5.347dbm 1 03374-0-024 marker 39.905000mhz ? 5.347dbm f i g u re 12. f ou t = 39.9 m h z , f c lk = 4 00 msp s , nbsfdr, 1 mhz center 80.25mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ? 4dbm pea k log 10db/ atten 10db mkr1 80.301mhz ?6.318dbm 1 03374-0-025 marker 80.301000mhz ? 6.318dbm f i g u re 13. f ou t = 8 0 . 3 m h z, fclk = 40 0 msps, nbsfdr, 1 mh z center 120.2mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ? 4dbm pea k log 10db/ atten 10db mkr1 120.205mhz ?6.825dbm 1 03374-0-026 marker 120.205000mhz ? 6.825dbm f i g u re 14. f ou t = 120 .2 mhz, f c lk = 400 msp s , nbsfdr, 1 mh z center 160.5mhz #res bw 30hz ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ? 4dbm pea k log 10db/ atten 10db mkr1 600khz ? 0.911db 1 03374-0-027 center 160.5000000mhz f i g u re 15. f ou t = 1 6 0 mh z, fclk = 40 0 msps, nbsfdr , 1 mh z
ad9951 rev. 0 | page 11 of 28 f i gure 16. r e sidua l p h ase n o is e w i th f ou t = 1 5 9 .5 mh z, f cl k = 400 msps ( g r een), 4 100 m s ps (red), and 20 20 msps (blue) f i gure 17. r e sidua l p h ase n o is e w i th f ou t = 9 . 5 m h z, f clk = 400 msps ( g r e e n ), 4 1 00 m s ps (r ed), and 20 2 0 m s ps (blue)
ad9951 rev. 0 | page 12 of 28 theory of operation componen t blocks dds cor e the o u t p u t f r e q uen c y ( f o ) of t h e dd s i s a f u nc t i on of t h e f r e - q u en c y o f t h e s y s t em clo c k (s y s clk), t h e val u e o f t h e f r e - qu e n c y tu n i ng word ( ft w ), a n d th e ca pa ci t y o f th e a c cum u la - tor ( 2 32 , in t h is c a s e ). t h e exac t re l a t i o n shi p is g i v e n b e lo w w i t h f s def i n e d as t h e f r e q uen c y o f s y sclk. () () 31 32 2 0 2 / = ftw with f ftw f s o ( ) ( ) 1 C 2 2 2 / C 1 32 31 32 < < = ftw with ftw f f s o the val u e a t t h e o u t p u t o f t h e phas e acc u m u l a to r is t r a n s l a t e d to a n am pli t ude va l u e v i a t h e c o s ( x) f u n c t i o n a l blo c k an d r o u t e d to t h e d a c . i n cer t a i n a p pli c a t ion s , i t is desi ra b l e t o fo r c e t h e o u t p ut sig n al t o zer o p h as e . s i m p l y s e t t in g t h e ft w t o 0 do es n o t acco m p lish t h is; i t o n ly r e su l t s in t h e dds c o r e h o ldin g i t s c u r r en t phas e v a lu e. t h u s , a c o n t ro l bit i s re q u i r e d to f o rc e t h e p h a s e a c c u m u - l a tor out p ut to z e ro . a t p o w e r - u p , t h e cle a r phas e ac c u m u la t o r b i t is s e t t o l o g i c 1, but t h e bu f f e r m e m o r y f o r t h i s bi t i s c l e a re d ( l o g i c 0 ) . t h e r e - f o re, up on p o we r - up , t h e p h a s e a c c u m u l a tor w i l l re m a i n c l e a r un til t h e f i rs t i/o upd a te is is s u ed . phase-locked loop (pll) the p ll al lo ws m u l t i p lica t i o n of th e refcl k f r e q uen c y . c o n - tr o l o f th e p l l is a c co m p li sh e d b y p r ogra m m i n g th e 5-b i t refclk m u l t i p lier p o r t io n o f c o n t r o l f u n c tion r e g i s t er n o . 2, bi ts <7:3 >. w h en p r og ra mm e d f o r val u es ra n g in g f r o m 0x 04 t o 0x14 (4 de cimal t o 20 de cimal), the pll m u l t i p lies the refclk in p u t f r e q u e nc y b y t h e c o r r e s p o nd i n g d e c i m a l v a lu e. h o we ve r , t h e max i m u m o u tpu t f r e q uen c y o f t h e pll is r e st r i c t e d to 400 mh z. w h enev er the p ll val u e is c h a n g e d , th e us er sh o u ld be a w a r e tha t tim e m u s t be allo ca t e d t o allo w th e pl l t o loc k (a p p r o x ima t e l y 1 m s ). the p ll is b y p a s s e d b y p r og ra mmin g a val u e o u tside t h e ra n g e o f 4 t o 20 (decimal). w h en b y p a s s e d , the p ll is s h u t do wn t o co n s er v e p o w e r . clock inpu t the ad9951 s u p p o r ts va r i o u s c l o c k metho d olog ies. s u p p o r t f o r dif f er en t i al o r si n g le-e n d e d in pu t clo c ks and ena b lin g o f a n on - c h i p o s c i l l a t o r and / or a ph a s e - l o c k e d l o op ( p l l ) m u lt ipl i e r a r e al l co n t r o l l ed via us er p r og ra mma b l e b i ts. th e ad9951 ma y b e c o n f i g u r e d i n o n e of s i x op e r a t i n g mo d e s to ge ne r a te t h e sys t em clo c k. th e m o des a r e conf igur e d usin g t h e c l kmo d e- s e lect pin, c f r1<4>, an d c f r2<7:3>. c o nn e c t i n g t h e ext e r - nal p i n clkmo d es elect to log i c h i g h ena b les th e o n -chi p cr ys tal os cil l a t or cir c ui t. w i t h t h e on-c hi p os cil l a t o r enab led , us ers o f th e ad9951 co nnec t an ext e r n al cr ys tal t o th e refcl k a nd refcl k b in p u ts t o p r o d uc e a lo w f r eq uenc y r e f e r e n c e c l o c k in t h e rang e o f 20 mh z t o 30 mh z. th e sig n al g e n e r a t e d b y t h e os ci l l a t o r is b u f f er e d b e for e i t is de l i v e r e d t o t h e r e s t o f t h e chi p . thi s b u f f er e d sig n al is a v a i la b l e v i a t h e cr y s t a l out pin. bi t c f r1<4> can b e us e d to ena b le or dis a b l e t h e b u f f er , t u r n in g o n o r o f f t h e syst em clo c k. th e os ci l l a t o r i t s e lf i s n o t p o w e r e d do w n in o r der to a v o i d lo n g st a r t u p t i m e s ass o c i - at e d w i t h t u r n i n g o n a c r y s t a l o s c i l l at o r . w r i t i n g c f r 2 < 9 > t o l o g i c h i g h enab les t h e cr ys t a l os ci l l a t o r o u t p ut b u f f er . l o g i c l o w a t cfr2<9 > dis a b l es t h e o s ci l l a t o r o u t p u t b u f f er . c o nn ec t i n g clkm o d es elect t o log i c lo w disa b l es t h e o n - c hi p osc i lla t o r a n d th e osc i lla t o r o u t p u t b u f f e r . w i th th e o s c i l l a t or d i s a bl e d , an e x te r n a l o s c i l l a t or m u st prov i d e t h e ref c lk and/or ref c lkb sig n a l s. f o r dif f er en t i a l o p er a t io n, t h es e pin s a r e dr i v en w i t h com p lem e n t a r y sig n als. f o r sin g le- en ded op era t ion, a 0.1 f c a p a ci t o r sh o u ld be co nnec t e d bet w een t h e un used p i n a n d t h e a n al og po w e r s u p p l y . w i th t h e ca p a c i t o r in place , th e c l o c k in p u t p i n b i as v o l t ag e is 1.35 v . i n addi t i o n , t h e p l l ma y b e us e d to m u l t i p l y t h e r e fer e n c e f r e q uen c y b y a n in teg e r val u e i n t h e ra n g e o f 4 t o 20. t a b l e 4 summa r i zes t h e clo c k mo des o f o p era t ion. n o te t h a t t h e pl l m u l t i p l i e r i s co n t r o ll ed via th e c f r 2 < 7 : 3 > b i t s , i n de pen d en t o f t h e cfr1 <4> b i t. table 4.clock i nput modes of operation cfr1<4 > c l k m o d e s e l e c t cfr2<7:3 > oscillator en abled? system c l ock frequency r a nge (mhz) low high 3 < m < 21 yes f clk = f osc m 80 < f clk < 400 low high m < 4 or m > 20 yes f clk = f osc 20 < f clk < 30 low low 3 < m < 21 no f clk = f osc m 80 < f clk < 400 low low m < 4 or m > 20 no f clk = f osc 10 < f clk < 400 h i g h x x n o f clk = 0 n/a
ad9951 rev. 0 | page 13 of 28 dac o u tp ut the ad9951 inco r p o r a t es a n in t e g r a t ed 14 -b i t c u r r en t o u t p u t da c . u n l i ke m o st d a cs, this o u t p ut i s ref e renc e d to a v dd , not a g nd . t w o c o m p l e me n t ar y output s prov i d e a c o mbi n e d f u l l - s c a l e output c u r r e n t ( i ou t ). dif f er en t i al o u t p uts r e d u c e t h e am o u n t o f co mm o n - m o d e n o is e t h a t mig h t b e p r es en t a t t h e d a c o u t p ut, o f fer i n g t h e ad v a n t a g e o f a n i n c r e a s e d sig n al -t o - n o is e ra t i o . the f u l l -s cale c u r r en t is con t r o l l ed b y a n ext e r n al r e sis t o r (r set ) co nne c t e d b e twe e n t h e d a c_r set p i n a nd t h e d a c g r o u nd ( a g n d _ d a c ) . t h e f u l l - s c a l e c u r r e n t i s prop or t i on a l to t h e re s i stor v a lu e a s f o l l ow s : out set i r / 19 . 39 = th e maxim u m fu l l -s cale o u t p u t c u r r en t o f t h e co m b i n e d d a c o u t p u t s i s 1 5 ma , b u t limi tin g th e o u t p u t t o 10 ma p r o v ide s th e b e s t s p ur io us- f r ee d y na mic ra n g e (s fd r) p e r f o r m a n c e . th e d a c ou t p u t c o m p l i anc e r a n g e is a v d d + 0 . 5 v t o a v dd C 0. 5 v . v o l t a g es de v e lo pe d b e yo n d t h is ra n g e wi l l ca us e e x ces s i v e d a c disto r t i o n a n d co u l d p o ten t ia lly da ma ge t h e d a c o u t p u t cir c ui tr y . p r o p e r a t t e n t io n s h o u ld be pa id t o th e l o ad t e r m i n a t io n t o k e ep th e o u t p u t v o l t a g e w i th i n th i s c o m p li a n ce ra n g e . serial io port th e ad9951 s e r i al p o r t is a f l exi b l e , syn c h r o n o u s ser i al co mm uni- ca ti o n s po r t th a t all o w s ea s y i n ter f a c e to man y i n d u st r y - s t a ndard m i c r o c on t r ol l e r s and m i c r opro c e ss or s. t h e s e r i a l i / o p o r t i s c o m - pa ti b l e w i th m o s t syn c h r o n o u s tr a n sf e r f o rm a t s, i n c l ud i n g bo th th e m o t o r o la 690 5/1 1 s p i ? a n d i n t e l? 8051 ss r p r o t o c ol s. the in te r f ac e a l lows r e ad/wr i te ac c e ss t o a l l reg i st e r s t h a t c o nf ig ur e th e ad9951 . m s b f i rs t o r ls b f i rs t tra n s f er f o r m a t s a r e s u p p o r t e d . th e ad9951 s s e r i al in t e rface po r t ca n be co n f ig ur ed as a sin g le p i n i/o (s di o), w h i c h a l lo ws a 2-wir e in t e rface o r tw o un idir ec t i o n a l p i n s fo r in/o u t (s di o/s d o), w h ic h in t u r n ena b les a 3-wir e in t e r - f a c e . t w o op t i ona l pi ns, io s y nc and cs , e n a b l e g r e a t e r f l e x i b i l i t y fo r sy ste m de s i g n in t h e a d 9 9 51. r e gis t er m a p an d d e s c ri ptions the r e g i s t er ma p is lis t e d i n t a b l e 5.
ad9951 rev. 0 | page 14 of 28 table 5. register map register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value <7:0> digital power- down not used dac power- down clock input power- down external power- down mode not used sync_clk out disable not used 0x00 <15:8> not used not used autoclr phase accum enable sine output not used clear phase accum. sdio input only lsb first 0x00 <23:16> automatic sync enable software manual sync not used 0x00 control function register no.1 (cfr1) (0x00) <31:24> not used load arr @ i/o ud osk enable auto osk keying 0x00 <7:0> refclk multiplier 0x00 or 0x01, or 0x02 or 0x03: bypass multiplier 0x04 to 0x14: 4 to 20 multiplication vco range charge pump current <1:0> 0x00 <15:8> not used high speed sync enable hardware manual sync enable crystal out pin active not used 0x00 control function register no. 2 (cfr2) (0x01) <23:16> not used 0x00 <7:0> amplitude scale factor register <7:0> 0x00 amplitude scale factor (asf) (0x02) <15:8> auto ramp rate speed control <1:0> amplitude scale factor register <13:8> 0x00 amplitude ramp rate (arr) (0x03) <7:0> amplitude ramp rate register <7:0> 0x00 <7:0> frequency tuning word no. 0 <7:0> 0x00 <15:8> frequency tuning word no. 0 <15:8> 0x00 <23:16> frequency tuning word no. 0 <23:16> 0x00 frequency tuning word (ftw0) (0x04) <31:24> frequency tuning word no. 0 <31:24> 0x00 <7:0> phase offset word no. 0 <7:0> 0x00 phase offset word (pow0) (0x05) <15:8> not used<1:0> phase offset word no. 0 <13:8> 0x00
ad9951 rev. 0 | page 15 of 28 control register bit descriptions control function register no. 1 (cfr1) the cfr1 is used to control the various functions, features, and modes of the ad9951. the functionality of each bit is detailed below. cfr1<31:27>: not used cfr1<26>: amplitude ramp rate load control bit cfr1<26> = 0 (default). the amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an i/o update input signal. cfr1<26> = 1. the amplitude ramp rate timer is loaded upon timeout (timer == 1) or at the time of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit cfr1<25> = 0 (default). shaped on-off keying is bypassed. cfr1<25> = 1. shaped on-off keying is enabled. when enabled, cfr1<24> controls the mode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high) cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on-off keying opera- tion. each amplitude sample sent to the dac is multiplied by the amplitude scale factor. see the shaped on-off keying sec- tion for details. cfr1<24> = 1. when cfr1<25> is active, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. toggling the osk pin high will cause the output scalar to ramp up from zero scale to the amplitude scale factor at a rate deter- mined by the amplitude ramp rate. toggling the osk pin low will cause the output to ramp down from the amplitude scale factor to zero scale at the amplitude ramp rate. see the shaped on-off keying section for details. cfr1<23>: automatic synchronization enable bit cfr1<23> = 0 (default). the automatic synchronization feature of multiple ad9951s is inactive. cfr1<23> = 1. the automatic synchronization feature of mul- tiple ad9951s is active. the device will synchronize its internal synchronization clock (sync_clk) to align to the signal pre- sent on the sync_in input. see the synchronizing multiple ad9951s section for details. cfr1<22>: software manual synchronization of multiple ad9951 cfr1<22> = 0 (default). the manual synchronization feature is inactive. cfr1<22> = 1. the software controlled manual synchroniza- tion feature is executed. the sync_clk rising edge is advanced by one sync_clk cycle and this bit is cleared. to advance the rising edge multiple times, this bit needs to be set for each advance. see the synchronizing multiple ad9951s sec- tion for details. cfr1<21:14>: not used cfr1<13>: auto-clear phase accumulator bit cfr1<13> = 0 (default), the current state of the phase accumu- lator remains unchanged when the frequency tuning word is applied. cfr1<13> = 1. this bit automatically synchronously clears (loads 0s into) the phase accumulator for one cycle upon recep- tion of an i/o update signal. cfr1<12>: sine/cosine select bit cfr1<12> = 0 (default). the angle-to-amplitude conversion logic employs a cosine function. cfr1<12> = 1. the angle-to-a mplitude conversion logic employs a sine function. cfr1<11>: not used cfr1<10>: clear phase accumulator cfr1<10> = 0 (default). the phase accumulator functions as normal. cfr1<10> = 1. the phase accumulator memory elements are cleared and held clear until this bit is cleared. cfr1<9>: sdio input only cfr1<9> = 0 (default). the sdio pin has bidirectional opera- tion (2-wire serial programming mode). cfr1<9> = 1. the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial programming mode). cfr1<8>: lsb first cfr1<8> = 0 (default). msb first format is active. cfr1<8> = 1. the serial interface accepts serial data in lsb first format. cfr1<7>: digital power-down bit cfr1<7> = 0 (default). all digital functions and clocks are active. cfr1<7> = 1. all non-io digital functionality is suspended, lowering the power significantly.
ad9951 rev. 0 | page 16 of 28 cfr1<6>: not used cfr1<5>: dac power-down bit cfr1<5> = 0 (default). the dac is enabled for operation. cfr1<5> = 1. the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power-down bit cfr1<4> = 0 (default). the clock input circuitry is enabled for operation. cfr1<4> = 1. the clock input circuitry is disabled and the device is in its lowest power dissipation state. cfr1<3>: external power-down mode cfr1<3> = 0 (default). the external power-down mode selected is the rapid recovery power-down mode. in this mode, when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock input circuitry are not powered down. cfr1<3> = 1. the external power-down mode selected is the full power-down mode. in this mode, when the pwrdwnctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. cfr1<2>: not used cfr1<1>: sync_clk disable bit cfr1<1> = 0 (default). the sync_clk pin is active. cfr1<1> = 1. the sync_clk pin assumes a static logic 0 state to keep noise generated by the digital circuitry at a mini- mum. however, the synchronization circuitry remains active (internally) to maintain normal device timing. cfr1<0>: not used, leave at 0 control function register no. 2 (cfr2) the cfr2 is used to control the various functions, features, and modes of the ad9951, primarily related to the analog sections of the chip. cfr2<23:12>: not used cfr2<11>: high speed sync enable bit cfr2<11> = 0 (default). the high speed sync enhancement is off. cfr2<11> = 1. the high speed sync enhancement is on. this bit should be set when attempting to use the auto- synchronization feature for sync_clk inputs beyond 50 mhz, (200 msps sysclk). see the synchronizing multiple ad9951s section for details. cfr2<10>: hardware manual sync enable bit cfr2<10> = 0 (default). the hardware manual sync function is off. cfr2<10> = 1. the hardware manual sync function is enabled. while this bit is set, a rising edge on the sync_in pin will cause the device to advance the sync_clk rising edge by one refclk cycle. unlike the software manual sync enable bit, this bit does not self-clear. once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. see the synchronizing multiple ad9951s section for details. cfr2<9>: crystal out enable bit cfr2<9> = 0 (default). the crystal out pin is inactive. cfr2<9> = 1. the crystal out pin is active. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a refer- ence frequency. the oscillator will respond to crystals in the range of 20 mhz to 30 mhz. cfr2<8>: not used cfr2<7:3>: reference clock multiplier control bits this 5-bit word controls the multiplier value out of the clock- multiplier (pll) block. valid values are decimal 4 to 20 (0x04 to 0x14). values entered outside this range will bypass the clock multiplier. see the phase-locked loop (pll) section for details. cfr2<2>: vco range control bit this bit is used to control the range setting on the vco. when cfr2<2> == 0 (default), the vco operates in a range of 100 mhz to 250 mhz. when cfr2<2> == 1, the vco operates in a range of 250 mhz to 400 mhz. cfr2<1:0>: charge pump current control bits these bits are used to control the current setting on the charge pump. the default setting, cfr2<1:0>, sets the charge pump current to the default value of 75 a. for each bit added (01, 10, 11), 25 a of current is added to the charge pump current: 100 a, 125 a, and 150 a.
ad9951 rev. 0 | page 17 of 28 other register descriptions amplitude scal e factor (asf) the a s f r e g i s t e r s t o r es t h e 2- b i t a u t o ram p ra te s p e e d val u e a nd t h e 14- b i t am pli t ude s c ale f a c t o r us e d i n t h e o u t p ut s h a p e d k e y i n g ( o s k ) o p e r at i o n . in au t o o s k o p e r at i o n , a s f < 1 5 : 1 4 > t e l l s t h e os k b l o c k h o w man y a m pli t ude s t eps t o t a k e fo r e a ch i n cr em en t o r d e cr e m en t . a s f< 13: 0 > se t s t h e maxi m u m v a l u e achie v ab le b y t h e os k in ter n a l m u l t i p lier . i n m a n u a l os k m o de , a s f<15: 14> has n o ef f e c t . a s f <13:0> p r o v ide t h e o u t p ut s c ale fac t o r dir e c t l y . i f t h e o s k ena b le b i t is cle a r e d , cfr1<25> = 0, this r e g i s t er has n o ef f e c t o n de vice op era t ion. amplitude ramp rate (arr) the a rr r e g i ster s t o r es t h e 8 - b i t am pli t ude ram p ra te us e d i n th e a u t o os k mo de . this r e g i ster p r og ra m s th e ra t e a t w h ic h t h e am pli t ude s c ale fac t o r co un t e r in cr e m e n ts o r de cr em e n ts. i f t h e o s k is s e t to ma n u a l m o de , o r if os k ena b l e is cle a r e d , t h is r e g i s t er has n o ef fe c t o n de vic e o p era t ion. frequency tun i ng word 0 (f tw0) t h e f r e q u e nc y tu n i ng word i s a 3 2 - bit re g i st e r t h a t c o n t ro l s t h e r a te of a c c u m u l a t i on i n t h e ph a s e a c c u m u l a tor of t h e dd s c o re . i t s sp e c if ic r o le is dep e n d e n t on t h e d e vice m o d e o f o p era t io n . phase offset w o rd (pow) the phas e o f fs et w o r d is a 14- b i t r e g i s t er t h a t s t o r es a phas e o f fs et val u e . this o f fs et val u e is adde d t o t h e o u t p u t o f t h e phas e a c c u m u la t o r t o o f fs et t h e cur r en t phas e o f t h e o u t p u t si g n al . th e exa c t val u e o f p h as e o f fs et is g i v e n b y t h e f o ll o w in g f o r m u l a: ? ? ? ? ? ? = 360 2 14 pow modes of operation single-tone m o de i n sin g le -t on e m o de , t h e d d s co r e us es a sin g le t u ni n g w o r d . w h a t e v er va l u e is s t o r e d i n f t w0 is s u p p li e d to t h e phas e acc u m u l a t o r . this va l u e can o n ly b e cha n ge d ma n u a l ly , w h ich is do ne b y wr i t i n g a ne w va l u e to f t w0 an d b y issuin g an i/o up d a te. p h as e ad j u s t m e n t is p o s s i b l e t h r o u g h t h e phas e o f fs et r e g i s t er . programming ad9951 features phase offset control a 14-b i t pha s e o f fs et () ma y b e adde d t o t h e o u t p u t o f t h e phas e acc u m u la t o r b y m e a n s o f t h e co n t r o l r e g i s t e r s . t h is fe a t ur e p r o v ides t h e us e r wi t h tw o di f f er en t m e t h o d s o f phas e co n t r o l. the f i rs t m e t h o d is a st a t ic phas e ad j u s t m e n t , w h er e a f i xe d phas e o f fs et is lo ade d i n t o t h e a p p r o p r i a te phas e o f fs et r e g i s t er a nd lef t u n c h a n g e d . th e r e s u l t is tha t t h e o u t p u t sig n al is o f fs et b y a co n s tan t ang l e r e la t i v e t o t h e n o minal sig n a l . this al lo ws t h e us er t o phas e alig n t h e d d s o u t p u t w i t h s o m e ext e r n al sig n al , if n e ces s a r y . the s e cond m e t h o d o f phas e con t r o l is w h er e t h e us er r e gu la rly u p da t e s t h e phas e o f fs et r e g i s t er vi a t h e i/ o p o r t . b y p r o p erly m o dif y in g t h e phas e o f fs et as a f u n c t i on o f t i me , t h e us er can i m p l em en t a p h a s e m o d u la t e d o u t p u t s i gn al . h o w e v e r , bo th t h e s p e e d o f t h e i / o p o r t a nd t h e f r e q uen c y o f s y sclk li mi t t h e r a te a t w h i c h ph a s e mo d u l a t i on c a n b e p e r f or me d. the ad9951 al lo ws f o r a p r og ra mma b l e con t in uo us zer o i n g o f t h e pha s e acc u m u l a to r as wel l as a cle a r an d r e le as e o r a u to- m a ti c z e r o i n g f u n c ti o n . e a c h f e a t ur e i s in d i v i d u all y co n t r o lled v i a t h e cfr1 b i ts. cfr1<13> is t h e a u t o ma t i c cle a r phas e ac- c u m u la t o r b i t. cfr1<10> cle a rs t h e phas e acc u m u la t o r an d h o lds t h e val u e t o zer o . c o ntinuous c l ea r bit the co n t in uo us c l ea r b i t is sim p l y a s t a t ic co n t r o l sig n al tha t , w h en ac t i v e hig h , h o lds t h e phas e acc u m u l a t o r a t zer o fo r t h e en t i r e t i me t h e b i t is ac t i v e . w h en t h e b i t g o es l o w , inac t i v e , t h e phas e ac c u m u l a tor i s a l l o we d to op e r a t e. c l ear an d r e l e as e fun c tion w h en s e t, t h e a u t o -cle a r phas e acc u m u l a t o r cle a rs a nd r e le as es t h e phas e acc u m u l a t o r u p on r e ceivin g an i/ o up d a te. th e a u t o ma ti c c l ea rin g fun c ti o n i s r e pea t ed f o r ev e r y s u b s eq uen t i/o upd a te u n til t h e a p p r o p r i a t e a u t o -c lea r c o n t r o l b i t is cl e a re d. shap ed on -of f keying t h e sh a p e d on - o f f ke y i ng f u nc t i on of t h e a d 9 9 5 1 a l l o w s t h e u s e r to c o n t ro l t h e r a m p - u p a n d r a m p - d ow n t i me of a n on - o f f emis sio n f r o m t h e d a c. this f u n c tio n is us ed in b u r s t tran s- m i s s i o n s o f d i g i tal da t a t o r e d u ce th e ad v e r s e s p ectral i m pa ct o f s h o r t, a b r u p t b u rs ts o f da t a . a u to a nd man u a l sha p e d on-o f f k e y i n g m o de s a r e su p p o r te d . the a u to mo de ge ne r a te s a l i ne ar s c a l e f a c t or a t a r a te de te r - mi n e d b y t h e am pli t ude ram p ra t e (ar r ) r e g i s t er co n t r o l l e d b y a n ext e r n al p i n (os k ). m a n u al m o de al lo ws the us er t o dir e c t l y co n t r o l t h e ou t p u t a m pl i t ude b y wr i t ing t h e s c al e fac t o r val u e in t o t h e am pli t u d e s c ale fac t o r (a s f ) r e g i s ter . t h e s h a p e d o n -o f f k e yin g f u n c t i o n ma y be b y p a s s e d (d isa b le d ) by c l e a r i n g t h e o s k e n a b l e bit ( c f r 1 < 2 5 > = 0 ) . t h e m o d e s a r e co n t r o lled b y tw o b i t s lo ca t e d in th e m o s t s i g- n i f i c a n t by te of t h e c o n t ro l f u nc t i on re g i ste r ( c f r ) . c f r 1 < 2 5 > i s th e s h a p ed o n - o f f k e yi n g e n a b le b i t . w h en cfr 1 < 25> i s set , th e o u t p u t scalin g fun c ti o n i s en a b led a n d c f r1< 25> b y pa s s e s th e fun c ti o n . cfr 1 < 24> i s t h e i n t e rn al s h a p ed o n - o f f k e yin g ac t i v e b i t. w h en cfr1<24> is s et, in ter nal s h a p e d o n -o f f k e ying m o de is ac ti ve; cfr1<24> is c l ea r e d , ext e r n al sha p e d o n -o f f k e ying mo de is ac t i v e . cfr1<2 4> is a d o n t c a r e if t h e sh a p e d o n -o f f k e yin g ena b le b i t (cfr1 < 25>) is c l ea r e d. th e p o w e r u p co ndi tion is s h a p ed on-o f f k e yin g dis a b l e d (cf r 1<25> = 0). f i g u r e 18 s h o w s th e b l ock dia g ra m o f th e o s k ci r c ui tr y .
ad9951 rev. 0 | page 18 of 28 auto sh aped on-off keying mode operati o n the a u t o s h a p e d o n -o f f k e y i n g m o de is ac ti ve when cfr1 <25 > a nd cfr1<24 > a r e s et. w h e n a u t o s h a p e d on- o f f k e yi n g m o de is ena b le d , a sing le s c a l e fac t o r i s in ter n a l ly ge ner a te d an d a p plie d t o t h e m u l t i p lier i n p u t fo r s c alin g t h e o u t p ut o f t h e dds c ore bl o c k ( s e e f i g u re 1 8 ) . t h e s c a l e f a c t or i s t h e output of a 14- b i t co un t e r t h a t in cr em en t s /d ecr e m e n t s a t a ra t e d e t e rm in e d b y t h e co n t e n ts o f t h e 8- b i t ou t p u t ra m p r a t e r e g i s t er . the s c ale fa ct o r i n cr ease s i f th e o s k p i n is h i gh a n d d e cr ea se s i f th e o s k p i n is lo w . th e s c ale fac t o r is an un sig n e d val u e s u c h tha t al l 0s m u l t i p l y t h e dds co r e o u t p u t b y 0 (d ecim al) a n d 0x3fff m u l - ti p l ies the d d s co r e o u t p u t b y 16383 (decimal ). f o r t h os e us ers w h o us e t h e f u l l a m pli t ude (14- b i ts) b u t ne e d fas t ram p ra t e s, th e in t e r n all y g e n e ra t e d scale f a ct o r s t ep size is co n t r o l l e d v i a t h e a s f < 15:14 > b i ts. t a b l e 6 des c r i b e s t h e in cr e m e n t/ de crem e n t st ep si ze o f t h e in t e r n al ly g e n e r a t e d s c ale fac t o r p e r th e as f<15:14> b i t s . a s p eci a l f e a t ur e o f th i s m o de is th a t t h e m a xim u m o u t p u t a m pli t ude al lo we d is limi t e d b y t h e con t e n ts o f t h e am pli t ude s c ale fac t o r r e g i s t er . this al lo ws t h e us er t o ra m p t o a val u e les s tha n f u l l s c ale . table 6. auto- s cale factor internal step siz e asf<15: 14> (binary) increment/decrement size 0 0 1 0 1 2 1 0 4 1 1 8 osk ram p rate timer t h e os k ra m p ra t e tim e r is a lo ad ab le d o wn co un t e r , wh ich ge ne r a te s t h e cl o c k s i g n a l to t h e 1 4 - bi t c o u n te r t h a t ge ne r a te s th e in t e rn al s c ale fa ct o r . t h e ra m p ra t e tim e r i s loa d ed wi th t h e v a l u e o f th e a s fr ev e r y ti m e th e co un t e r r e a c h e s 1 (d ecim al). this lo ad and c o un tdo w n o p er a t io n co n t i n ues fo r as lo n g as t h e ti m e r i s e n a b le d , unle s s th e tim e r i s f o r c ed t o loa d b e f o r e r e a c h - in g a co u n t o f 1. i f th e loa d o s k ti m e r b i t (c fr 1< 26> ) i s se t , t h e ra m p ra t e tim e r i s l o a d e d up o n an i / o u p d a t e or up on re a c h i ng a v a lu e of 1 . t h e r a m p t i me r c a n b e l o a d e d b e f ore re a c h i ng a c o u n t of 1 by th r e e m e t h o d s . m e t h o d on e is b y cha n g i n g t h e os k i n p u t p i n. w h en t h e o s k in p u t p i n cha n ges s t a t e , t h e a s f r val u e is lo ade d in t o t h e ra m p ra t e tim e r , w h i c h th en p r oce e d s t o co un t d o wn a s n o rm al . t h e seco n d m e t h o d in wh ich t h e sw eep ram p ra t e tim e r can be lo ade d b e fo r e r e achin g a co un t o f 1 is if t h e lo ad osk t i m e r b i t (cfr1<26>) is s et an d a n i/o up d a te is is s u ed . t h e las t m e t h o d in wh ich t h e sw eep ra m p ra t e tim e r ca n b e l o a d e d b e f ore re a c h i ng a c o u n t of 1 i s w h e n goi n g f rom t h e i n a c ti v e a u t o s h a p e d o n - o f f k e yi n g m o d e t o th e a c ti v e a u t o s h a p e d on-o f f k e ying m o de; t h a t is, w h en t h e s w e e p ena b le b i t is be in g se t. 03374-0-005 osk pin load osk timer cfr1<26> sync_clk auto desk enable cfr1<24> to dac auto scale factor generator ramp rate timer clock dds core osk enable cfr<25> amplitude scale factor register (asf) 0 0 1 01 01 hold inc/dec enable out cos(x) amplitude ramp rate register (asf) up/dn data load en f i g u re 18. o n - o f f shaped k e y i ng , bl oc k d i ag r a m
ad9951 rev. 0 | page 19 of 28 extern al sh ap ed on -off key i ng mode o p e r ation the ext e r n al s h a p e d o n -o f f k e y i n g m o de is enab led b y wr i t in g cfr1<25> t o a l o g i c 1 a nd wr i t in g cfr1<24 > t o a l o g i c 0. w h en conf igur e d fo r ext e r n al s h a p e d o n -o f f k e yin g , t h e co n t e n t o f t h e as fr b e com e s t h e s c ale fac t o r for t h e da t a p a t h . the s c ale f a c t o r s a r e sy n c hr o n i z e d t o s y n c _cl k v i a t h e i/o upd a te f u n c tio n al i t y . synchroniz ati o n; register u p dates (i/o u p date) functionality of the s y nc_cl k and i/o up date da t a in t o the ad9951 is sy n c hro n o u s t o the s y n c _cl k sig n al (s u p plie d ext e r n al ly t o t h e us er o n t h e s y n c _ c lk p i n). th e i/ o u p d a t e p i n i s sa m p le d o n th e ri s i n g ed g e o f th e sy n c _ c l k . i n ter n a l ly , s y sc lk is fe d to a divide -b y - 4 f r e q uen c y divid e r to p r o d uce t h e s y n c _cl k sig n al. th e s y n c _cl k sig n al is p r o - vide d to t h e us e r o n t h e s y n c _ c lk p i n. thi s e n a b les sy n c hr o - n i z a t i o n of e x te r n a l h a rdw a re w i t h t h e d e v i c e s i n te r n a l cl o c k s . t h i s i s a c c o m p l i she d by f orc i n g an y e x te r n a l h a rdw a re to o b t a i n i t s t i min g f r o m s y nc_cl k . the i/o up d a te sig n al co u p le d wi t h s y n c _clk is us ed t o tran sf er in t e r n al b u f f er co n t en ts in t o t h e con t r o l r e g i s t ers o f t h e de vice . the com b ina t ion o f t h e s y nc_cl k and i/o upd a te p i n s p r o v ides t h e us er wi t h co n s t a n t l a te n c y r e la t i ve t o s y s c lk, an d als o en s u r e s phas e c o n t i n u i t y of t h e an a l o g output s i g n a l w h e n a n e w tu n i ng word o r phas e o f fs et val u e is as s e r t e d . f i gur e 19 demo n s t r a t e s a n i / o upd a te t i m i ng c y cle a n d sy n c hr o n iz a t ion. n o te s to s y nc hroni z a t i o n l o g i c : 1) the i / o up d a te s i g n a l i s e d g e de te c t e d to ge ne r a te a sin g le r i sin g edg e c l o c k sig n al t h a t dr i v es t h e r e g i s t er ba n k f l o p s. th e i/o up d a te sig n al has n o con s t r a i n t s on d u ty c y cle. th e mi ni m u m lo w t i m e o n i/o upd a t e is o n e s y nc_ c l k cl o c k c y cl e. 2) the i/o upd a te p i n is s et u p a nd h e ld a r o u nd t h e r i sin g edg e o f s y n c _clk and has zer o h o ld tim e and 4 n s s e t u p ti m e . 03374-0-006 sysclk sdi sync_clk disable 10 0 sclk to core logic cs osk d q profile<1:0> d q i/o update d q 4 sync_clk gating edge detection logic register memory i/o buffer latches f i gure 19. i/o s y n c hr oniz ation block d i agr a m
ad9951 rev. 0 | page 20 of 28 sync_clk sysclk ab data 2 data 3 data 1 data in registers data in i/o buffers data 1 data 2 data 3 i/o update the device registers an i/o update at point a. the data is transferred from the asynchronously loaded i/o buffers at point b. 03374-0-007 f i gure 20. i/o s y n c hr oniz ation t i ming d i ag r a m synchronizing multipl e ad9951s the ad9951 p r o d uc t al lo ws easy syn c hr o n iza t io n o f m u l t i p le ad9951s. th ere a r e thr e e m o des o f syn c hr o n iza t ion a v a i la b l e t o t h e us er : a n a u t o ma t i c sy n c hro n iza t ion m o de , a s o f t w a r e c o n t ro l l e d m a n u a l s y nch r on i z at i o n mo d e , an d a h a rdw a re co n t r o l l ed man u al sy n c hr o n iza t io n m o de . i n al l cas e s, w h en a us er wa n t s t o s y n c hr o n ize tw o or m o r e de v i ces, t h e fol l o w in g c o ns ide r a t ions m u st b e obs e r v e d . f i rst , a l l u n i t s m u st share a co m m o n clo c k s o ur ce. t r ace le n g t h s an d p a t h i m p e dance o f t h e clo c k t r e e m u s t b e desig n e d t o k e ep t h e phas e de l a y o f t h e dif - fer e n t clo c k b r an ch es as clos ely ma tch e d as p o ssi b l e. s e cond , t h e i/o upd a te sig n al s r i sin g e d g e m u st b e prov i d e d s y nc h ro- n o us ly t o al l de vices i n t h e sys tem. f i nal l y , r e gar d les s o f t h e in t e r n a l sy n c hr o n iz a t ion m e t h o d us e d , t h e d v d d _i/o su p p ly s h o u ld b e s et t o 3.3 v fo r al l de vices t h a t a r e t o b e sy n c hr o n i z e d . a v d d and d v d d s h o u l d b e lef t a t 1.8 v . i n a u t o ma t i c sy n c hr o n iz a t ion m o d e , o n e d e v i ce is ch os e n as a m a s t e r ; th e o t h e r d e vi ce (s ) w i ll be s l a v ed t o th i s m a s t e r . w h en co nf igur e d in t h is m o de , t h e sl a v es wi l l a u t o ma t i ca l l y sy n c hr o- nize t h eir in t e r n al c l o c ks t o t h e s y nc_clk o u t p u t sig n al o f th e mas t er de vice . t o en t e r a u t o ma t i c syn c hr o n i z a t i o n m o de , s e t t h e s l a v e device s a u t o ma tic sy n c hr oniza t ion b i t (cf r 1<23> = 1). c o nn e c t t h e s y n c _i n in p u t(s) t o t h e mas t er s y n c _ c lk o u t p ut. th e sla v e de vic e w i l l con t i n uo us ly u p da t e t h e phas e r e la ti o n s h i p o f i t s s y n c _ c l k un til i t i s i n p h ase wi th t h e s y nc_in in pu t , w h ich is t h e s y n c _ c lk o f t h e mast er d e vic e . w h e n a tte m p t i ng to s y nchroni z e d e v i c e s r u nn i n g a t s y s c l k s p eeds b e yo nd 250 ms ps, th e hig h sp ee d sy n c enhan c em en t ena b le b i t s h o u l d b e s et (cfr2 < 11> = 1). i n s o f t w a re m a n u a l s y n c h ron i z a t i o n m o d e , t h e u s e r f orc e s t h e de vice t o ad vance t h e s y n c _c lk r i sin g e d g e o n e s y scl k c y cle (1/4 s y nc_clk p e r i o d ). t o ac t i v a te t h e ma n u al sy n c hr o- niza t i on m o de , s et t h e s l a v e de v i ce s s o f t wa r e ma n u al sy n c h r o n i - za tio n b i t (cfr1 < 22> = 1 ) . th e b i t (cfr 1<22> ) w i l l be c l ea r e d i m m e d i a t e l y . t o a d v a n c e th e ri s i n g ed g e o f th e s y n c _ c l k m u l t i - p l e ti m e s , th i s b i t w i ll n eed t o be s e t m u l t i p le ti m e s . i n h a rd w a re m a n u a l s y n c h ron i z a t i o n m o d e , t h e s y n c _ i n in p u t p i n is co n f igur e d such t h a t i t wi l l n o w adv a n c e t h e r i sin g ed g e o f th e s y n c _ c l k s i gnal e a c h tim e t h e d e v i ce d e t e cts a r i sin g e d g e o n t h e s y nc_in p i n. t o p u t t h e de vice in t o ha rd - w a re m a n u a l s y nch ron i z a t i o n mo d e , s e t t h e h a rdw a re m a n u a l syn c hr o n iza t ion b i t (cf r 2<10> = 1). u n li k e t h e s o f t wa r e ma n - ual sy n c hr o n iza t io n b i t, t h is b i t do es n o t s e lf- c le a r . on ce t h e h a rdw a re m a n u a l s y nch ron i z a t i o n mo d e i s e n a b l e d, a l l r i s i ng e d g e s dete c t e d o n t h e s y n c _i n in p u t wi l l c a u s e t h e de vi ce t o ad van c e t h e r i sin g e d g e o f t h e s y n c _ c lk b y on e s y scl k c y cle un t i l t h is ena b le b i t is cle a re d (cfr2<10 > = 0). using a single crystal to dri v e multipl e a d 9951 clock inp u ts the ad9951 cr ys tal os cil l a t o r ou t p u t sig n al is a v a i lab l e o n t h e cr y s t a l o u t p i n, ena b l i n g on e cr ys t a l t o dr iv e m u l t i p le ad9951s. i n o r der t o dr i v e m u l t i p le ad9951s wi t h on e cr ys tal, th e cr y s t a l o u t p i n o f th e ad9951 u s in g th e ext e r n a l c r ys tal s h o u ld b e co nn ec t e d t o t h e refclk in p u t o f t h e o t h e r ad 9951. the cr y s t a l o u t pin is st a t i c un t i l t h e cfr 2 <9> b i t is s e t, ena b lin g t h e ou t p u t . th e dr i v e st r e n g t h o f t h e c r y s t a l o u t p i n is typ i cal l y v e r y l o w , s o this sig n al s h o u l d b e b u f f er ed p r io r to u s i n g i t to dr i v e an y l o ads . serial port operation w i t h t h e ad99 51, t h e inst r u c t io n b y t e sp e c if ie s r e ad/ w r i t e o p era t ion an d reg i s t er addr es s. s e r i al o p er a t io ns o n t h e a d 995 1 o c c u r o n ly a t t h e r e g i s t er le ve l, n o t t h e b y te le ve l. f o r t h e ad9951, the s e r i al p o r t con t r o l l er r e cog n izes t h e in s t r u c t io n b y t e r e g i s t er addr es s an d a u t o ma t i c a l l y g e n e r a t e s t h e p r o p er r e g i s t er b y t e addr es s. i n addi t i on, t h e con t r o l l er exp e c t s t h a t al l b y t e s o f th a t r e g i s t e r will b e a c ce s s ed . i t i s a r e q u i r ed th a t all b y t e s o f a r e g i s ter be acces s e d d u r i n g s e r i al i/o o p era t io ns, wi t h o n e excep t io n. th e i o s y nc f u n c tio n can be us e d t o a b o r t a n i / o o p era t io n, t h er eb y al lo win g les s t h a n al l b y t e s to b e ac c e ss e d .
ad9951 rev. 0 | page 21 of 28 ther e a r e tw o phas es t o a comm unic a t ion c y cle w i t h t h e ad9951. p h as e 1 is th e in s t r u c t io n c y c l e , whic h is th e wr i t in g o f a n ins t r u c t io n b y t e in t o th e ad9951, co in ciden t wi th t h e f i rs t eig h t s c lk r i si n g e d g e s. th e ins t r u c t io n b y t e pr o v ides t h e ad9951 s e r i al p o r t co n t r o l l er wi t h inf o r m a t ion r e ga r d in g t h e da ta tra n s f e r c y c l e , wh i c h i s p h a s e 2 o f t h e c o m m u n i c a t i o n c y c l e . th e p h as e 1 in s t r u c t i o n b y t e de f i n e s w h et h e r t h e u p co min g d a t a t r a n sfer is r e ad o r wr i t e and t h e s e r i al addr es s of t h e r e g i s t er b e i n g access e d . [n o t e t h a t t h e s e r i al addr es s o f t h e r e g i st er be in g a cce ssed is n o t th e sa m e a d d r e s s a s t h e b y t e s t o be wr i t t e n. s e e t h e e x a m ple o p era t io n s e c t ion fo r det a i l s.] the f i rs t eig h t s c lk r i sin g e d g e s o f e a ch co mm unica t io n c y cle a r e us ed t o wr i te th e in s t r u c t io n b y t e in t o t h e ad9951. th e r e ma inin g s c l k e d g e s a r e fo r p h as e 2 o f t h e c o mm uni c a t io n c y c l e . p h as e 2 is th e ac t u al da t a tra n sf er between the ad9951 a nd t h e sys t e m co n t r o l l er . th e n u m b er o f b y t e s t r a n sfer r e d d u r i n g p h as e 2 o f t h e co mm uni c a t ion c y cle is a f u n c t i on o f t h e r e g i s t e r bein g ac ces s ed . f o r e x a m p l e , wh en acces s i n g th e c o n t r o l f u nc t i on r e g i ster n o . 2, w h ich is t h re e b y t e s w i de , phas e 2 re qu ires th a t th r e e b y t e s be tra n s f e r r e d . i f a cce s s i n g th e fr e q ue n c y tu n i ng w o r d , w h ich is fo ur b y t e s wide , phas e 2 r e q u ir e s t h a t fo ur b y t e s be tra n s f e r r e d . a f t e r tra n s f e rri n g all da t a b y t e s pe r th e in s t r u c- t i o n , t h e co mm unica t io n c y cle is co m p let e d . a t th e com p letio n o f a n y co mm unic a t ion c y c l e , th e ad9951 se ri al po r t c o n t r o l l e r e x pect s th e n e xt ei gh t ri s i n g s c l k ed g e s t o b e t h e i n st r u c t io n b y t e o f t h e n e xt comm un ica t ion c y cle . a l l da ta in p u t t o t h e ad9951 is r e g i s t er ed on t h e r i sin g edg e o f sclk. al l da ta is dr i v en o u t o f t h e ad9951 on t h e fal l in g edge of s c l k . f i g u re 2 1 t h rou g h f i g u re 2 4 are u s e f u l i n u n d e r s t a n d - in g the g e n e ral o p era t ion o f th e ad9951 s e r i al p o r t . 03374-0-008 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s clk sdio data transfer cycle cs f i gure 21. s e ri al p o r t write ti ming C c l o ck sta l l l o w 03374-0-009 i 6 i 5 i 4 i 3 i 2 i 1 i 0 don't care i 7 instruction cycle s clk sdio data transfer cycle d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 d o 7 d o 6 sdo cs f i g u re 22. 3-w i r e s e ri al p o r t r e ad ti m i ng C c l o ck st al l l o w 03374-0-010 i 6 i 5 i 4 i 3 i 2 i 1 d 5 d 4 d 3 d 2 d 1 d 0 i 0 d 7 d 6 i 7 instruction cycle s cl k sdio data transfer cycle cs f i gure 23. s e ri al p o r t write ti ming C c l o ck sta l l h i gh 03374-0-011 i 6 i 5 i 4 i 3 i 2 i 1 d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 i 0 d o 7 d o 6 i 7 instruction cycle s clk sdio data transfer cycle cs f i g u re 24. 2-w i r e s e ri al p o r t r e ad ti m i ng c l o ck st a l l h i g h
ad9951 rev. 0 | page 22 of 28 instruction byte the instruction byte contains the following information: table 7. msb d6 d5 d4 d3 d2 d1 lsb r/wb x x a4 a3 a2 a1 a0 r/wbbit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. x, xbits 6 and 5 of the instruction byte are dont care. a4, a3, a2, a1, a0bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclkserial clock. the serial clock pin is used to synchronize data to and from the ad9951 and to run the internal state machines. sclk maximum frequency is 25 mhz. csbchip select bar. csb is active low input that allows more than one device on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio serial data i/o. data is always written into the ad9951 on this pin. however, this pin can be used as a bidirectional data line. bit 7 of register address 0x00 controls the configuration of this pin. the default is logic 0, which configures the sdio pin as bidirectional. sdoserial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9951 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high imped- ance state. iosyncit synchronizes the i/o port state machines without affecting the addressable registers contents. an active high in- put on the iosync pin causes the current communication cycle to abort. after iosync returns low (logic 0), another communication cycle may begin, starting with the instruction byte write. msb/lsb transfers the ad9951 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 0x00 <8> bit. the default value of control register 0x00 <8> is low (msb first). when control register 0x00 <8> is set high, the ad9951 serial port is in lsb first format. the instruction byte must be written in the format indicated by control register 0x00 <8>. if the ad9951 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the next lesser significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9951 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9951 must be (will be) in lsb first order. example operation to write the amplitude scale factor register in msb first format, apply an instruction byte of 0x02 (serial address is 00010(b)). from this instruction, the internal controller will generate an internal byte address of 0x07 (see the register map) for the first data byte written and an internal address of 0x08 for the next byte written. since the amplitude scale factor register is two bytes wide, this ends the communication cycle. to write the amplitude scale factor register in lsb first format, apply an instruction byte of 0x40. from this instruction, the internal controller will generate an internal byte address of 0x08 (see the register map) for the first data byte written and an internal address of 0x07for the next byte written. since the amplitude scale factor register is two bytes wide, this ends the communication cycle. power-down functions of the ad9951 the ad9951 supports an externally controlled or hardware power-down feature as well as the more common software pro- grammable power-down bits found in previous adi dds products. the software control power-down allows the dac, pll, input clock circuitry, and digital logic to be individually powered down via unique control bits (cfr1<7:4>). with the exception of cfr1<6>, these bits are not active when the externally con- trolled power-down pin (pwrdwnctl) is high. external power-down control is supported on the ad9951 via the pwrdwnctl input pin. when the pwrdwnctl input pin is high, the ad9951 will enter a power-down mode based on the cfr1<3> bit. when the pwrdwnctl input pin is low, the external power-down control is inactive.
ad9951 rev. 0 | page 23 of 28 when the cfr1<3> bit is 0 and the pwrdwnctl input pin is high, the ad9951 is put into a fast recovery power-down mode. in this mode, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock input circuitry is not powered down. when the cfr1<3> bit is high, and the pwrdwnctl input pin is high, the ad9951 is put into the full power-down mode. in this mode, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the individual power-down bits (cfr1<7>, <5:4>) are invalid (dont care) and unused. when the pwrdwnctl input pin is low, the individual power-down bits control the power-down modes of operation. note that the power-down signals are all designed such that a logic 1 indicates the low power mode and a logic 0 indicates the active or powered up mode. table 8 indicates the logic level for each power-down bit that drives out of the ad9951 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. layout considerations for the best performance, the following layout guidelines should be observed. always provide the analog power supply (avdd) and the digital power supply (dvdd) on separate supplies, even if just from two different voltage regulators driven by a common supply. likewise, the ground connections (agnd, dgnd) should be kept separate as far back to the source as possible (i.e., separate the ground planes on a local- ized board, even if the grounds connect to a common point in the system). bypass capacitors should be placed as close to the device pin as possible. usually, a multitiered bypassing scheme consisting of a small high frequency capacitor (100 pf) placed close to the supply pin and progressively larger capacitors (0.1 f, 10 f) further away from the actual supply source works best. table 8. power-down control functions control mode active description pwrdwnctl = 0 cfr1<3> dont care software control digital power-down = cfr1<7> dac power-down = cfr1<5> input clock power-down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power-down mode digital power-down = 1b1 dac power-down = 1b0 input clock power-down = 1b0 pwrdwnctl = 1 cfr1<3> = 1 external control, full power-down mode digital power-down = 1b1 dac power-down = 1b1 input clock power-down = 1b1
ad9951 rev. 0 | page 24 of 28 suggested application circuits 03374-0-012 lpf ad9951 refcl k rf/if input modulated/ demodulated signal f i g u re 25. sy nch r o n ized l o f o r upconversion / d own conversion 03374-0-013 filter phase comparator loop filter ad9951 tuning world ref signal vco f i g u re 26. d i g i t a l l y p r og r a m m ab le d i v i de -by-n f u nc t i on i n pll 03374- 0- 015 saw crystal frequency tuning word phase offset word 2 i/i-bar baseband frequency tuning word phase offset word 1 q/q-bar baseband sync in ad9951 dds refclk refclk refclk lpf sync out crystal out ad9951 dds iout iout lpf iout iout rf out f i g u re 27. t w o a d 9 9 5 1 s sy nch r o n i z ed to pr o v ide i and q c a rr ie r s wi th inde p e ndent p h a s e o f fse t s fo r nulli ng
ad9951 rev. 0 | page 25 of 28 outline dimensions bottom view (pins up) top view (pins down) 0.50 bsc 0.27 0.22 0.17 9.00 bsc sq 7.00 bsc sq 37 48 1 13 12 24 25 36 view a 0.75 0.60 0.45 view a 1.05 1.00 0.95 7 3.5 0 seating plane 0.15 0.05 exposed pad 2.00 sq 1.20 ma x compliant to jedec standards ms-026-abc f i g u re 28. 4 8 -l ead thin plas t i c q u ad flat p a ck ag e , e x pos e d p a d [ t qf p/e p ] ( s v - 48) d i m ens i o n s s h o wn in m i l l i m eters esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. w a rnin g p l e a se n o t e t h a t t h is d e vice in i t s curr en t f o rm d o es n o t m e et a n alog d e vices s t a n da r d r e q u ir e m en ts f o r es d as m e as ur e d a g a i n s t t h e ch a r g e d de vice m o de l ( c d m ). a s s u ch , s p ecial c a r e s h o u ld b e use d wh en h a n d lin g this p r o d uc t, es p e ciall y in a m a n u fac t urin g en vir o n m en t. a n alog d e vic e s wi ll p r o v i d e a m o r e es d h a r d y p r o d u c t in th e n e a r fu t u r e a t whic h ti m e thi s wa rn- in g wi l l b e r e m o v e d f r o m this da t a s h e e t. ordering guide model temperature r a nge package descri ption package outlin e ad9951ysv C40c to +105c 48-lead thin plastic qu ad flat package, expo sed pad, tqfp/e p sv-48 ad9951ysv-ree l7 C40c to +105c 48-lead tqfp/ep (500 piece ree l 7) sv-48 a d 9 9 5 1 / p c b e v a l u a t i o n boar d
ad9951 rev. 0 | page 26 of 28 notes
ad9951 rev. 0 | page 27 of 28 notes
ad9951 rev. 0 | page 28 of 28 notes ? 2003 an alog devic e s, inc. all rights res e rve d . tra d em arks a n d re gis- tered trade m arks are the property of their respective owners . c03359-0-11/03(0)

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